This invention relates to a semiconductor device and methods of fabricating the same and, more particularly, to a semiconductor device having multi-gate insulating layers and methods of fabricating the same.
Most semiconductor devices such as semiconductor memory devices or semiconductor logic devices use a plurality of MOS transistors in order to increase integration density and reduce power consumption. Generally, an oxide layer having a unique thickness is used as the gate insulating layers of all the MOS transistors in the semiconductor device. However, non-volatile memory devices such as electrically programmable read only memory (EPROM) devices, electrically erasable programmable read only memory (EEPROM) devices or flash memory devices require both low voltage MOS transistors operating in a read mode and high voltage MOS transistors operating in an erase or a program mode. Accordingly, at least two kinds of MOS transistors are formed in the non-volatile memory device.
Voltages applied to the high voltage MOS transistor are higher than those applied to the low voltage MOS transistor. Thus, the high voltage MOS transistor should be designed to be different from the low voltage MOS transistor. For example, the gate insulating layer of the high voltage MOS transistor should be thicker than that of the low voltage MOS transistor in order to achieve reliability at the high voltage. As a result, in such devices, it is required to form at least two kinds of gate insulating layers having different thickness from each other, i.e., multi-gate insulating layers, in order to fabricate the non-volatile memory device.
A method of fabricating a non-volatile memory device is taught in U.S. Pat. No. 5,723,355 entitled xe2x80x9cMethod to incorporate non-volatile memory and logic components into a single sub-0.3 micron fabrication process for embedded non-volatile memory,xe2x80x9d by Chang et al., which is hereby incorporated herein by reference. This method includes the step of sequentially forming a tunnel oxide layer of a cell transistor and a polysilicon layer for a floating gate on an entire surface of a semiconductor substrate. The polysilicon layer and the tunnel oxide layer are successively patterned to expose the substrate in a high voltage MOS transistor region and the substrate in a logic MOS transistor region. A gate insulating layer for the high voltage MOS transistor is formed at the surface of the exposed semiconductor substrate. The gate insulating layer in the logic MOS transistor region is selectively removed to expose the substrate in the logic MOS transistor region. A gate insulating layer for the logic MOS transistor is formed at the surface of the exposed substrate in the logic MOS transistor region.
According to the U.S. Pat. No. 5,723,355, the tunnel oxide layer in the cell transistor region can be prevented from being in direct contact with a first photoresist pattern exposing the high voltage transistor region and the logic transistor region. Thus, it is possible to prevent the tunnel oxide layer from being contaminated due to the first photoresist pattern. However, the gate insulating layer formed in the high voltage transistor region is in direct contact with a second photoresist pattern exposing only the logic transistor region. Thus, the gate insulating layer for the high voltage transistor can be contaminated by the second photoresist pattern. As a result, the reliability of the gate insulating layer for the high voltage transistor is degraded.
FIG. 1 is a top plan view showing a portion of typical non-volatile memory device having multi-gate insulating layers. In the drawing, the reference character xe2x80x9caxe2x80x9d represents a high voltage transistor region in the peripheral circuit region and the reference character xe2x80x9cbxe2x80x9d represents a cell array region. The cell array region b may correspond to a low voltage transistor region in the peripheral circuit region.
Referring to FIG. 1, a first active region 1a and a second active region 1b are disposed in the high voltage transistor region a and in the cell array region b, respectively. A first gate pattern GP1 runs across the first active region 1a. A first gate insulating layer is interposed between the first gate pattern GP1 and the first active region 1a. The first gate pattern GP1 comprises a first gate electrode, a first inter-gate dielectric layer and a first dummy gate electrode, which are sequentially stacked.
Similarly, a second gate pattern GP2 runs across the second active region 1b. The second gate pattern GP2 comprises a floating gate FG, a second inter-gate dielectric layer and a control gate electrode CG, which are sequentially stacked. A second gate insulating layer, i.e., a tunnel oxide layer, is interposed between the floating gate and the second active region 1b. The second gate insulating layer is thinner than the first gate insulating layer. The floating gate FG should be separated from an adjacent floating gate (not shown) and is overlapped with a portion of the control gate electrode CG. Thus, two patterning processes are required in order to form the floating gate FG. Specifically, the floating gate is formed through a first patterning process for exposing an isolation region 3 adjacent to the second active region 1b and a second patterning process for defining the control gate electrode CG.
In the event that the cell array region b corresponds to the low voltage transistor region in the peripheral circuit region, the second gate pattern GP2 comprises a second gate electrode, a second inter-gate dielectric layer and a second dummy gate electrode which are sequentially stacked. At this time, the second gate electrode is completely overlapped with the second dummy gate electrode.
FIGS. 2-8, 9A, 9B, 10, 11, 12A and 12B are cross sectional views for illustrating a fabrication method of a semiconductor device according to conventional technology. In each drawing, the reference character xe2x80x9caxe2x80x9d represents the high voltage transistor region of FIG. 1 and the reference character xe2x80x9cbxe2x80x9d represents the cell array region of FIG. 1. Also, FIGS. 2-8, 10 and 11 are cross sectional views along the line Ixe2x80x94I or the line IIxe2x80x94II of FIG. 1. In addition, FIGS. 9A and 12A are cross sectional views along the line Ixe2x80x94I of FIG. 1, and FIGS. 9B and 12B are cross sectional views along the line IIxe2x80x94II of FIG. 1.
Referring to FIG. 2, a first gate insulating layer 13, i.e., a gate insulating layer for a high voltage transistor, is formed on an entire surface of a semiconductor substrate 11. The first gate insulating layer 13 is formed by thermally oxidizing the semiconductor substrate 11, for example, a silicon substrate. The first gate insulating layer 13 is formed to a thickness of at least 300 A in order to obtain the endurance to high voltages such as a program voltage and/or an erase voltage of 15 volts to 20 volts.
A fist photoresist pattern 15 covering the high voltage transistor region a is formed. The first gate insulating layer 13 is wet-etched using the first photoresist pattern 15 as a etching mask, thereby exposing the substrate 11 of the cell array region b.
Referring to FIG. 3, the first photoresist pattern 15 is removed. A thermal oxidation process is applied to the resultant structure where the first photoresist pattern 15 is removed, to thereby form a second gate insulating layer 17, e.g., a tunnel oxide layer of cell transistor on the exposed substrate of the cell array region b. The second gate insulating layer 17 is formed to a thin thickness of 100 A or the less. At this time, a surface step difference T exists between the first gate insulating layer 13 and the second gate insulating layer 17 as shown in FIG. 3. The surface step difference T corresponds to at least a thickness difference between the first and second gate insulating layers 13 and 17.
A first conductive layer 19 and a chemical mechanical polishing (CMP) stopper layer 21 are sequentially formed on the entire surface of the resultant structure where the first and second gate insulating layers 13 and 17 are formed. The first conductive layer 19 is formed of doped polysilicon layer and the CMP stopper layer 21 is formed of silicon nitride layer.
Referring to FIG. 4, the CMP stopper layer 21 and the first conductive layer 19 are successively patterned to form a first pad pattern in the high voltage transistor region a and a second pad pattern in the cell array region b. The first pad pattern comprises a first conductive layer pattern 19a and a CMP stopper layer pattern 21a which are sequentially stacked on a predetermined region of the high voltage transistor region a. Similarly, the second pad pattern comprises a first conductive layer pattern 19b and a CMP stopper layer pattern 21b which are sequentially stacked on a predetermined region of the cell array region b.
The first and second gate insulating layers 13 and 17 are etched using the first and second pad patterns as etching masks to expose the substrate 11. Subsequently, the exposed substrate 11 is dry-etched, thereby forming a trench region 23 defining at least one first active region 1a in the high voltage transistor region a and at least one second active region 1b in the cell array region b. At this time, the sidewall of the trench region 23 may show a sloped profile as shown in FIG. 4. This is because polymer is adsorbed on the sidewall of the etched region during the dry-etching process.
The resultant structure having the trench region 23 is thermally oxidized to form a thermal oxide layer 25a at the sidewall and bottom of the trench region 23. At this time, a thermal oxide layer 25b may also be formed at the sidewalls of the first and second conductive layer patterns 19a and 19b. The thermal oxide layer 25a is formed in order to repair the etch damage applied to the substrate 11 during the dry-etching process for forming the trench region 23.
Referring to FIG. 5, an insulating layer filling the trench region 23 is formed on the entire surface of the resultant structure where the thermal oxide layer 25a is formed. The insulating layer is planarized until the CMP stopper layer patterns 21a and 21b are exposed, to thereby form an insulating layer pattern 27 in the trench region 23. At this time, the CMP stopper layer pattern 21a in the high voltage transistor region a is more polished as compared to the CMP stopper layer pattern 21b in the cell region b. This is due to the step difference T described in connection with FIG. 3. Thus, a CMP stopper layer pattern 21axe2x80x2 remaining in the high voltage transistor region a becomes thinner than the CMP stopper layer pattern 21b remaining in the cell array region b. As a result, a first depth T1 from the top surface of the insulating layer pattern 27 to the top surface of the first gate insulating layer 13 is shallower than a second depth T2 from the top surface of the insulating layer pattern 27 to the top surface of the second gate insulating layer 17.
Referring to FIG. 6, after removing the CMP stopper layer patterns 21axe2x80x2 and 21b, the insulating layer pattern 27 is recessed to form an isolation layer 27a (or 27b). At this time, it is required to accurately control the recessing process. Specifically, in case that a first isolation layer 27a a top surface 27xe2x80x2 of which is higher than that of the first gate insulating layer 13 is formed by under-recessing process, a stringer may be left between the adjacent floating gates to be formed in a subsequent process.
Alternatively, in case that a second isolation layer 27b a top surface 27xe2x80x3 of which is lower than that of the first gate insulating layer 13 is formed by over-recessing process, thinning effect of the first gate insulating layer 13 is occurred. In other words, a dielectric breakdown characteristic between the first active region 1a and a gate electrode of the high voltage transistor to be formed in a subsequent process is degraded. In particular, in the event that the top surface 27xe2x80x3 of the second isolation layer 27b has the same height as the top surface of the second gate insulating layer 17, it is possible to completely remove the stringer between the adjacent floating gates. In this case, however, the dielectric breakdown characteristic of the high voltage transistor is remarkably degraded.
FIGS. 7, 8, 9A and 9B are cross sectional views for illustrating problems of conventional technology in more detail, in the case in which the top surface of the first isolation layer 27a has the same height as the top surface of the first gate insulating layer 13.
Referring to FIG. 7, a second conductive layer 29 is formed on the entire surface of the resultant structure where the first isolation layer 27a is formed. A second photoresist pattern 31 covering the high voltage transistor region a and the second active region 1bis formed on the second conductive layer 29.
Referring to FIG. 8, the second conductive layer 29 is etched using the second photoresist pattern 31 as a etching mask, to thereby form a second conductive layer pattern exposing the first isolation layer 27a in the cell array region b. The second conductive layer pattern comprises a second conductive layer pattern 29a covering the entire surface of the high voltage transistor region a and a second conductive layer pattern 29b covering the second active region 1b. An inter-gate dielectric layer 33 and a third conductive layer 35 are sequentially formed on the entire surface of the resultant having the second conductive layer patterns 29a and 29b. 
Referring to FIGS. 9A and 9B, the third conductive layer 35, the inter-gate dielectric layer 33, the second conductive layer patterns 29a and 29b, and the first conductive layer patterns 19a and 19b are anisotropically etched, thereby forming a first gate pattern GP1 crossing over the first active region 1a and a second gate pattern GP2 crossing over the second active region 1b. At this time, stringer 19s exists on the edge of the second active region 1bbetween the adjacent second gate patterns. The stringer 19s is formed due to the sloped sidewall of the first conductive layer pattern 19b. As the top surface of the first isolation layer 27a becomes higher, it is more difficult to remove the stringer 19s. 
The first gate pattern GP1 comprises a first gate electrode 30a, a first inter-gate dielectric layer 33a and a first dummy gate electrode 35a which are sequentially stacked. Also, the first gate electrode 30a comprises a first conductive layer pattern 19axe2x80x2 covering a portion of the first gate insulating layer 13 and a second conductive layer pattern 29axe2x80x2 running over the first conductive layer pattern 19axe2x80x2. Similarly, the second gate pattern GP2 comprises a floating gate FG, a second inter-gate dielectric layer 33b and a control gate electrode CG which are sequentially stacked. Also, the floating gate FG comprises a first conductive layer pattern 19bxe2x80x2 covering a portion of the second gate insulating layer 17 and a second conductive layer pattern 29bxe2x80x2 covering the first conductive layer pattern 19bxe2x80x2. 
In addition, in the event that a silicon nitride spacer (not shown) is formed on the sidewalls of the first and second gate pattern GP1 and GP2 using the conventional manner, a spacer residue 37 is formed on the sidewall of the stringer 19s as shown in FIG. 9A. This is because a step difference exists between the top surface of the second active region 1b and the top surface of the first isolation layer 27a adjacent to the second active region 1b. Accordingly, in case that a contact hole, e.g., a borderless contact hole, is formed on the second active region 1b in a subsequent process, an area of the second active region 1b to be exposed by the contact hole is reduced.
FIGS. 10, 11, 12A and 12B are cross sectional views for illustrating problems of conventional technology in more detail, in the case in which the top surface of the second isolation layer 27b has the same height as the top surface of the second gate insulating layer 17. Referring to FIGS. 10, 11, 12A and 12B, the first gate pattern GP1 and the second gate pattern GP2 are formed using the same manner as that described in connection with FIGS. 7, 8, 9A and 9B. In this case, even if the sidewall of the first conductive layer patterns 19a and 19b has the sloped profile, no stringer may be formed at the edge of the second active region 1b. This is because the top surface of the second isolation layer 27b has the same height as that of the second gate insulating layer 17. However, as shown in FIG. 12B, an effective thickness of the first gate insulating layer 13 is relatively reduced at the edge portion W of the first gate insulating layer 13.
As described above, according to the conventional technology, it is difficult to determine an optimal condition for recessing the insulating layer pattern in the trench region. Even though the trench region shows a vertical sidewall profile, the top surface of the isolation layer should be higher than that of the first gate insulating layer in order to avoid the thinning effect of the first gate insulating layer. If the step difference between the first and second gate insulating layers is increased, a process margin for recessing the insulating layer pattern is reduced. In the meantime, in the case in which the sidewall of the trench region shows a severe slope, the top surface of the isolation layer should be lower than that of the first gate insulating layer in order to suppress the occurrence of the stringer. However, if the top surface of the isolation layer is lower than that of the first gate insulating layer, the effective thickness of the first gate insulating layer is reduced.
It is therefore an object of the present invention to provide semiconductor device having high reliability by minimizing the step difference between the multi-gate insulating layers having different thicknesses from each other.
It is another object of the present invention to provide methods of fabricating a semiconductor device, which can increase the process margin of the recessing process for forming an isolation layer by minimizing the step difference between the multi-gate insulating layers having different thicknesses from each other.
It is still another object of the present invention to provide methods of fabricating a semiconductor device, which can prevent the stringer from being formed between the neighboring gate electrodes.
It is still another object of the present invention to provide methods of fabricating a semiconductor device, which can improve the dielectric breakdown characteristic of the multi-gate insulating layers having different thicknesses from each other.
According to one aspect of the present invention, the semiconductor device includes a plurality of active regions defined by an isolation region formed at a predetermined region of a semiconductor substrate. The plurality of the active regions comprise at least one first active region and at least one second active region. A top surface of the first active region is lower than that of the second active region. The first and second active regions are covered with a first gate insulating layer and a second gate insulating layer, respectively. The first gate insulating layer is thicker than the second gate insulating layer. An isolation region is formed on the semiconductor substrate between the plurality of active regions. A bottom of the isolation region is lower than the surface of the first active region. The isolation region is filled with an isolation layer which covers an entire sidewall of the first gate insulating layer and the second gate insulating layer.
In one embodiment, the step difference between the top surfaces of the first and second gate insulating layers is less than the thickness difference between the first and second insulating layers.
Also, in one embodiment, the bottom of the isolation region is lower than the top surface of the first active region. The isolation region can be a trench region etched in a predetermined region of the semiconductor substrate.
To achieve the above objects, the method according to one embodiment of the present invention includes the steps of forming a first gate insulating layer a bottom surface of which is lower than a main surface of a semiconductor substrate at a predetermined region of the semiconductor substrate. A second gate insulating layer which is thinner than the first insulating layer is formed at the main surface of the substrate adjacent to the first gate insulating layer. A first conductive layer and a chemical mechanical polishing (CMP) stopper layer are sequentially formed on the entire surface of the resultant having the first and second gate insulating layers. The CMP stopper layer, the first conductive layer, the first and second gate insulating layer, and the substrate are successively etched to form an isolation region, e.g., a trench region defining a first active region under the first gate insulating layer and a second active region under the second gate insulating layer. An insulating layer pattern is formed inside the isolation region. The patterned CMP stopper layer is then removed. The insulating layer pattern is recessed to form an isolation layer.
The first and second gate insulating layers are can be formed of a thermal oxide layer.
The insulating layer pattern can be recessed so that the entire sidewalls of the first and second gate insulating layers are still covered with the isolation layer.
To achieve the above objects, the method according to another embodiment of the present invention includes the steps of forming a plurality of pad patterns on a semiconductor substrate. The substrate is then etched using the pad patterns as etching masks, thereby forming a trench region defining at least one first active region and at least one second active region. An insulating layer pattern is formed in the trench region. The pad pattern on the first active region is selectively removed to expose the first active region. A first gate insulating layer is formed at the surface of the first active region. A bottom surface of the first gate insulating layer can be lower than the top surface of the second active region. The pad pattern on the second active region is then removed to selectively expose the second active region. A second gate insulating layer which is thinner than the first gate insulating layer is formed at the surface of the second active region.
The bottom surface of the first gate insulating layer can be lower than that of the second gate insulating layer.
Also, the first and second gate insulating layer can be formed of a thermal oxide layer.